Detailed Trace Modeling

For low pin count power packages, and QFNs when modelled with low pin count, it is unacceptably inaccurate to assume that the top signal layer copper coverage is uniformly distributed.

For these packages, the traces are explicitly represented in the following scenarios:

• 2R Compact Modeling

The traces are modelled explicitly on the top (signal) layer of the board, which improves the accuracy of the Rjb value. Users are therefore restricted from setting the Coverage% for the Top Layer. See "Submitting a Two-Resistor Compact Model Job".

• Setting up a Test Environment

When placing these packages in a Test Environment, the traces are modelled explicitly on the top (signal) layer of the board (and thus included in the downloadable PDML to provide a more accurate model). Users are therefore restricted from setting the Coverage% or the Layer Type for the Top Layer. See Step 1 of “Using the JEDEC Test Environment Wizard”.

The applicable packages are:

• Power/Discrete Packages:

• TO263

• Thin TO263

• TO252

• SOT89

• SOT23

• SOT223

• LFPAK

• PowerPak

• Chip Scale Packages:

• QFN

Based on the following restriction:

No. of Leads on Top/Bottom (MD) + No. of Leads on Left/Right (ME) < 20

Note
	For through-hole package types TO220 and TO247, traces on the Top signal layer for test environments created for these packages will NOT have the traces modelled explicitly on the Top Layer. The leads may or may not rest on the top of the board. Some may be embedded into the board, others may not make contact with the top layer at all.